Based lot size for minimizing the cycle time

Based on the journal with the title which is a simulated model for cycle time reduction by acquiring optimal lot size in size in semiconductor manufacturing. The objective of this journal is to develop a model which can find the optimal lot size for minimizing the cycle time which under different bottleneck loading environments. In this journal, a typical wafer fabrication process flow contain 300 to 500 operation steps which required over 30 to 45 days to complete it. This complicated operation requirements which consist of reentrant flow, queue-time limit, batch or splitting operations. Besides that, this complicated operation also will consist of shop uncertainties which is machine breakdown, rework, and random yield all this problem will cause the production planning and control activities become very difficult.
Furthermore, 24 wafers per lot was commonly used in wafer fabrication, this is because of the past equipment limitation and process technology. So, nowadays the wafer sizing policy is still fixed at the 24 wafers for one lot and putting in one cassette in most wafer fabrication. Just In Time (JIT) philosophy said that a smaller lot size can speed up the work-in-process (WIP) movement. Because of this philosophy a shorter production cycle time will result from a lower WIP level. From this journal, the author used the simulation methodology to do the cycle time analysis. This journal is motivated by a need of minimum effort to enhance the cycle time performance in manufacturing.
First of all, the project began with the problem statement of how to find the optimal lot size for minimizing the cycle time under different bottleneck utilization conditions. The realistic data of this simulation experiments is from a Taiwan semiconductor fabrication. In this simulated model, the lot size in one cassette is adjusted downward by one piece at a time from initial lot size of 24 pieces. There have five steps to conduct this simulation. Step 1 it is setting the lot size factor under different conditions. Step 2 is start the simulation with initial parameters. Step 3 is collect the data. Step 4 is reduce the lot size by one piece of wafer and repeat it from step 2. Lastly, step 5 is obtain the optimal lot size. When the lot size is decreased, the WIP will become more balance. Therefore, the utility of bottleneck tool will become more higher than expected. The feedback from the manufacturing managers mention that a wafer releasing rate which cannot more than 88% of bottleneck utility. If the wafer releasing rate is more than 88% of bottleneck utilization, the actual bottleneck utility will frequently exceed 100%. However, when releasing rate is less than 60%, it means no tools will have chance to meet 100% utility. Thus, there is no bottleneck will occur in this production line.
In addition, this simulation model is then simulate by four type of machine. This is to find out which machine is more suitable for the wafer fabrication manufacturing. This is because some machines can be operated in different processes and different processes on one machine will result a different average processing time for each wafer or lot on machine. Machine type A, type B and type C is one lot enters the machine at a time. For type A, each individual wafer is processes independently. This machine is capable of processing several wafers concurrently. The processing of one wafer does not depend on the completion of others wafer, as the result the total processing time of the lot is proportional to the lot size. For type B, each individual wafer is process accordingly. The processing time minus a constant in proportional to the lot size. For type C, all wafers in a lot are processed together simultaneously. The processing time of this machine is fixed. For type D, it required several lots enter the machine at a time. The processing time is fixed and is not related to the quantity of wafers and lots. In order to minimize the throughput, the turn ratio and utilization of this type of machine should be carefully analyzed. To analyzed the loading of bottleneck equipment, the simulation team set the value of 88% to be the upper loading level and 60% to be lower loading level. Thus, to get the differences between the upper loading level and lower loading level they set a third loading level to be 70%. This three loading are set for bottleneck analysis.
From this simulation experiments, the optimal lot sizes under different wafer releasing rates are obtained. As compared with the average cycle time time at a lot size of 24, the average cycle time reduction percentages are 10.94%, 9.93% and 7.00% for the loading level of 60%, 70% and 88% respectively. As a result, the smaller the lot size and the shorter the cycle time can be obtained when the system loading level is lower. In this study, the lot size with the shortest corresponding cycle time is picked as the best one which is 10, 12 and 16 for wafer releasing levels at 60%, 70% and 88% of bottleneck capacity respectively. The curve of the cycle times to the corresponding lot size is plotted in figure 1. It show that the greater the excess capacity, the smaller the lot size that can be applied and the shorter the cycle time which can be obtained. On the other hand, when the lot size smaller, the bottleneck utilization will increase under the same wafer releasing rate, it shown in figure 2. this is because the greater the setup, the more the bottleneck capacity is consumed and this will influence the cycle time to become bigger.

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