Design of Low Power High Speed SRAM Architecture using SK-LCT Technique
Manjith.R, Pousia.S
Abstract— In many VLSI chips, Static Random
Access memory (SRAM) has become an important component due to their large
storage capacity and small access time. Low power adequate memory design is one
of the most challenging issues in SRAM architecture. As the technology node
scaling down, leakage power consumption has become a significant problem. There
are various power gating schemes available in the literature such as sleep
technique, stack technique, sleepy stack technique, sleepy keeper technique,
lector technique, foot switch technique, double switch technique and
transmission switch technique for leakage power reduction. In this paper a new
power gating technique namely sleepy keeper leakage control transistor
technique (SK-LCT) is proposed for a low power SRAM architecture design. The
SRAM architecture has two main components namely SRAM cell and sense amplifier.
The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier
for a new low power high speed SRAM architecture design. Simulation is done
using Tanner EDA tool in 180nm technology and the results obtained shows a
significant improvement in leakage power consumption and speed.
Index Terms— SRAM,
SK-LCT Technique, Tanner EDA
I. INTRODUCTION
Very Large Scale Integration is
the process of creating an Integrated Circuit by combining thousand of
transistors
into a single chip. Rapid growth in VLSI fabrication process results in the
increase of the densities of integrated circuit by scaling down the technology.
With the advancement in technology that are happening in the world, the demand
for large storage of data is
increasing
in a way that needs to be faster than the existing technologies (Yeal 1998). Simultaneously, increasing of power
dissipation has become the major obstacle against further development of VLSI
circuits. Power consumption due to memory accesses in a
computing system often constitutes a dominant
portion of the total power consumption (F.Catthoor et al 1998).
SRAM is an important part of most of the digital chips which
consumes a large percent of power of each
chip (G.Pasandi et al 2003),
so decreasing the power of SRAM can lead to a decrease in the overall power of chips.
Due to quadratic relation between power and supply voltage of transistors (J.M.
Rabaey 2013), one effective and common method to reduce the power consumption
is to decrease the supply voltage.
Due to the strong demand of the SRAM memory in mobile products, System On-Chip
(SoC) & high performance VLSI circuits, the reduction of power consumption
is very important.
In
this paper, a new power gating technique namely SK-LCT Technique is used in the
design of SRAM cell and sense Amplifier which can be used for various
applications. The proposed SRAM architecture using SK-LCT technique has several
advantages over the conventional SRAMs design like improved read and write
ability which are achieved with a higher read speed and less energy
consumption.
II.
SLEEPY KEEPER LEAKAGE CONTROL TRANSISTOR
TECHNIQUE (SK-LCT TECHNIQUE) FOR LOW POWER HIGH SPEED SRAM ARCHITECTURE
SK-LCT Technique is the
combination of both Sleepy Keeper and LECTOR Technique. By combining these two
techniques, the delay & power of the SRAM Architecture can be further
reduced and the data retention can be maintained.
Fig.1
shows the SK-LCT Technique. Here, leakage control transistor (PMOS & NMOS)
is added in between the pull up and pull down network. Both PMOS and NMOS are
tied up parallel to preserve the stable retention in standby mode. The gate of
PMOS is connected with pull down network and gate of NMOS is connected with
pull up network. Here, the parallel connected PMOS and NMOS Transistor is
placed between pull up network and VDD & pull down network and VSS. In
sleep mode, additional NMOS is the only terminal between pull up network &
VDD and additional PMOS is the only terminal between pull down network &
VSS. The Figure4.1 shows the SK-LCT Technique.
Fig.1: SK-LCT Technique
The SRAM cell and Sense Amplifier
are the two main peripheral components of the SRAM Architecture; by the
optimized design of these two components low power & high speed memory
architecture can be obtained. SRAM Architecture can be designed by using SK-LCT
Technique.
By using this SK-LCT Technique,
leakage power of the memory can be further reduced with the optimized speed.
The Figure4.3 shows the Block Diagram of SRAM Architecture using SK-LCT
Technique.
III. DESIGN OF SRAM ARRAY
SRAM block diagram is shown in Figure1.1. It
consists of SRAM cell, precharge circuit, sense amplifier and row/ column
decoder and write driver circuit. The address decoders (also known as row
decoders) translate the binary address into a unary address exactly one word in
the core is selected. The address inputs are used to connect or select a memory
location within the memory device. The number of memory address pins found on
the memory device is determined by the number of memory locations found within
it. The data I/O connections are the
points at which data are entered for storage or extracted for reading. The bit
lines are read by circuits that sense the value on the line; amplify it to
speed it up and restore the signal to the proper voltage levels.
Figure1.1 SRAM Block Diagram
SRAMs can be organized as bit-oriented or word-oriented. In a
bit-oriented SRAM, each address accesses a single bit whereas in a
word-oriented memory, each address accesses a word of n bits. Here, SRAM cells are
arranged in an array of horizontal rows and vertical columns. In array
architecture, there are 2N rows that are called as word lines and 2M columns
that are called as bit lines. So, the total number of memory cells in the array
is 2(N+M). For fast read and write operation separate write driver circuit and
sense amplifier dedicated to each column. The components of SRAM building block
are as follows,
Ø SRAM
cell
Ø Pre-Charge
Circuit
Ø Sense
Amplifier
Ø Decoder
Ø Write
Driver Circuit
A. Design of Sram Cell Using SK-LCT Technique
B.Design of Sense Amplifier Using SK-LCT
Technique
B.
Domino CMOS Wallace Tree Decoder
C. Precharge Circuit
The precharge circuit is the main component
that is used in SRAM array. Precharge circuit consists of three PMOS
transistors. Two upper transistors are used for precharging and the lower one
is used for equalization. The main role of precharge circuit is to charge both
the bitlines up to VDD before a read and write operations. Each column has a
single precharge circuit in the array. The Figure1.3 shows the Precharge circuit.
Figure1.3 Precharge circuit
IV . SIMULATION RESULT
WL
BLB
BL
WRITE
BL
BLB
OUT
CONCLUSION
A Low power and high speed SRAM
architecture was designed using sleepy keeper leakage control transistor
technique (SK-LCT). SRAM cell and sense amplifier are the two main peripheral
components of the SRAM architecture which were designed using SK-LCT technique
for new low power high speed memory architecture. SRAM cell design using the
proposed SK-LCT technique saves 57.53% of power and 44.70% of delay. Similarly,
the sense amplifier design using the proposed SK-LCT technique saves 93.65% of power
and 95.26% of delay compared to conventional method. In the design of 1 bit
SRAM architecture, SK-LCT technique saves 23.54% of power and 38.64% of delay
& in the design of 4 bit SRAM architecture, SK-LCT technique saves 32.15%
of power and 53.07% of delay. Thus from the simulation results it was observed
that the proposed SK-LCT technique provides a low power high sped SRAM
architecture.
FUTURE WORK
In 1 bit & 4bit SRAM
Architecture there is no need of decoder to select the address line. But, in
the case of 8 bit, 16 bit and 32 bit SRAM Architecture there is a need of
address decoder to select the address line. The work can be further extended by
designing efficient Address Decoder and 8 bit, 16 bit and 32 bit SRAM
Architecture is designed using SK-LCT Technique which can be used in various
applications such as PC, Personal Communications, Consumer Electronics and
other fields.
