Standard Cell Library
Standard cells are designed based on area, performance and
power. The architecture will be decide by cell height which is based on pitch.
The metal track, ? ratio, pitch, and possible PMOS width and NMOS width
constant for particular library.
Pitch is the distance between two metal tracks.
width + Via overhead + Metal-to-metal spacing
Standard Height of Cells = Pitch * (M-1)
represents the number of tracks.
? is the ration between the PMOS width and NMOS width.
Standard cell library contains cells of different threshold devices (eg-
Standard Vt and Hight Vt) and different drive strength (multiple fingering).
Different category of
Cells in universal Library
Basic gated (NOT, AND, OR, NAND, NOR, XOR, XNOR)
Half Adder & Full Adder
Metal Ecoable cells
Flops (D Flip flop and Scan-able flop with
Spare Cells (Fillers, Tap cells, Decaps.. etc)
Boolean functional cells
Power management cells (Isolation cell, Level
Shifter, Power gate/switch)
cells are used to provide substrate connection and avoid latch-up. The cells
used to connect p-substrate top VSS and n-well to VDD.
filler cells are converted to accomplish any functionality are called metal ECO
cells. The size of these cells is more in comparison to normal cells of same
cells are used to provide power rail continuousness. This cells also contain p
substrate & n-well.
Cells (Decap cells)
used in design between power and ground rails. These cells behaves like a
battery when drops present in power rail and maintain the voltage across rails.
These cells aids IR drop issue and removes glitches in power.
End cap cells
added near the end of rows to terminate the rows properly.
are 2 type of TIE cell: – TIE High (give output VDD) & TIE Low (give output
In design, some cell input requires
a logic 0 or logic 1 value. Rather than providing connection to VSS/VDD rails,
you connect them to TIE cells. Tie cells used to avoid direct connection from
power rails to protect cell from breakage.